1. Field of the Invention
The present invention relates to a semiconductor device including sense amplifiers and a method of controlling such a semiconductor device.
2. Description of Related Art
One typical semiconductor device including sense amplifiers is a dynamic semiconductor storage device, for example. The semiconductor storage device has sense amplifiers connected to bit line pairs that are connected to memory cells. The sense amplifier amplifies a small potential voltage difference output from a memory cell to the bit line pair to read data (memory cell information) from the memory cell. As semiconductor storage devices have been integrated to a higher degree in recent years, their storage capacities have increased, but requirements call for reduced electric power consumption and operation at higher speeds.
An effective way to reduce the electric power consumption of a semiconductor storage device is to lower the operating voltage of the internal circuits of the semiconductor storage device. For example, if an external power supply voltage of +1.8 V is applied to a semiconductor storage device, then a voltage lower control circuit in the semiconductor storage device generates internal power supply voltage VINTS of +1.1 V, for example, from the external power supply voltage, and internal power supply voltage VINTS is supplied to a memory cell array (including a plurality of memory cells, a decoder for accessing the memory cells, and sense amplifiers for sensing memory cell information stored in the memory cells). Internal power supply voltage VINTS is a charging voltage for a bit line corresponding to information “1”, and is also a high-potential power supply voltage for the sense amplifier which detects the potential voltage of the bit line. If internal power supply voltage VINTS is lowered to reduce the charging voltage for the bit line, then according to the known ½ equalizing scheme, the power supply voltage for the sense amplifier is lowered, and the sensing time is increased. The sensing time refers to the time required after the sense amplifier has started to amplify the potential voltage difference (differential potential) between the bit lines of the bit line pair until the potential voltage difference increases to a prescribed potential voltage difference which is regarded as including a substantially constant value. The prescribed potential voltage difference (the difference between the low bit line potential voltage and the high bit line potential voltage) is of a value which is 95% of internal power supply voltage VINTS, for example.
When reading data from a semiconductor storage device, the general practice is have a word line become active so as to select a memory cell and to transmit the information stored in the memory cell and to bit lines, which initiates operation of a sense amplifier, and thereafter to select a Y-selection signal line with a Y decoder at the time the output potential voltage from the sense amplifier is established, which results in decoding the potential voltage difference between the bit lines and which is output from the sense amplifier. If the sensing time is increased, then because the potential voltage difference between the bit lines is read when the potential voltage difference is not yet sufficiently large, the potential voltage difference cannot be properly read. Consequently, it is necessary to increase the time required after the word line is selected until the Y decoder decodes the potential voltage difference. This means a reduction in the rate at which can be read data from the semiconductor storage device.
In order to reduce the sensing time for realizing high-speed operation of the semiconductor storage device, it has been customary to supply overdrive voltage VOD, that is higher than internal power supply voltage VINTS (VOD>VINTS), to the sense amplifier to increase the VGS (gate-to-source voltage) supplied to each transistor of the sense amplifier with overdrive voltage VOD, thereby operating the sense amplifier at a high speed. Such a process is referred to as an overdrive technique. The overdrive voltage is applied in the initial period of the initial access phase of the semiconductor storage device, for example.
The overdrive technique is described in Japanese Laid-Open Patent Application No. 2001-266573A (hereinafter referred to as “Patent document 1”), for example. Patent document 1 (FIGS. 3, 4, and 11) discloses an internal power supply circuit for generating internal power supply voltage VINTA, which comprises differential amplifier (operational amplifier) 52 for amplifying the difference between reference voltage VREF and internal power supply voltage VINTA, transistor 51 energizable by an output signal from differential amplifier 52, transistor 51 including a source supplied with an external power supply voltage and a drain outputting internal power supply voltage VINTA, and transistor 53 for forcibly connecting the output of differential amplifier 52 to a ground potential voltage when overdrive signal VOP is “high”, turning on transistor 51 to connect the line of internal power supply voltage VINTA (VINTS) and the line of the external power supply voltage to each other.
During a period in which overdrive signal VOP is “high”, the internal power supply circuit disclosed in Patent document 1 connects the line of internal power supply voltage VINTA to the line of the external power supply voltage, thereby overdriving the power supply voltage supplied to a sense amplifier. During a period in which overdrive signal VOP is “low”, the drain of transistor 51 outputs internal power supply voltage VINTA which is equal to reference voltage VREF.
As described above, Patent document 1 reveals that overdrive signal VOP is rendered “high” only during a certain period at the time when the sense amplifier starts its sensing process (initial sensing period). Usually, a one-shot pulse signal is used as overdrive signal VOP. The pulse duration of the one-shot pulse signal varies with PVT (process, voltage, temperature) variations. If overdrive signal VOP is shorter than the designed time, then the sensing time of the sense amplifier is prolonged. If overdrive signal VOP is longer than the designed time, then since the period in which the bit line voltage that is higher than a given voltage (reference voltage VREF) is elongated, this results in an increase in the electric power consumption of the semiconductor storage device. Accordingly, the internal power supply circuit disclosed in Patent document 1 is problematic in that it fails to provide a stable overdrive effect.
The internal power supply circuit disclosed in Patent document 1 is arranged such that it controls the differential amplifier to equalize internal power supply voltage VINTA and reference voltage VREF to each other after the end of the overdrive period. Therefore, transistor 51 consumes an amount of electric power which is commensurate with the potential voltage difference between the external power supply voltage and the internal power supply voltage VINTA. Since transistor 51 that supplies internal power supply voltage VINTA needs to be increased in size to deal with an overdrive period (initial sensing period) in which the load current is of a relatively large value, the electric power consumption of differential amplifier 52 which energizes transistor 51 accordingly is necessarily large.